Optimal DFT Design (Design for Testability) Solutions in 16nm, 7nm and below Chips

Design for Testability (DFT), is one of the effective ways to overcome power consumption challenges and huge data volumes in the testing process after production, which has grown dramatically in lower geometry node designs. DFT is becoming a key factor that saves higher design cost, higher power consumption, increasing execution testing time, chip area, pin counts, and other new fault types at small geometries in the testing phase itself.

DFT architecture approach is very easy to deploy, and also accelerates the development of a higher-quality test infrastructure at a lower cost. The advanced built-in technology enables testability for analog and mixed signal designs with limited digital inputs. Let’s understand how the below mentioned parameters optimize the DFT architecture to overcome challenges (including timing, area, and power):

1. Reduced pin count testing (RPCT) for Low pin-counts and low-cost testers

The semiconductor designs are getting more complex, owing to the need for lower geometries like 28nm, 16nm, 7nm, and beyond, even while the number of I/O pins on the processor increases. As transistor count increases exponentially, which affects the cost involved in enhancing testers, and types of test patterns (more logic gates to be tested) applied in multiple test cycles to achieve high test quality.

To limit the use of number of pin-counts, testers, and reduction in the overall product cost in a more efficient manner, DFT engineers are turning to new testability techniques to apply on a growing number of pin counts, and scan patterns in an efficient manner, such as reduced pin-count testing (RPCT).

Reduced low pin count testing is an effective solution that allows the application of at-speed test patterns using low-cost testers that are very pin-limited and enables improvements in coverage and implementation testing time with minimal impact on design.

Therefore, DFT engineers become capable for testing the I/O logics in a limited scan standard in order to achieve maximum fault coverage and increasingly adopting very low cost testers to keep the hardware design cost low.

2. Use of DFT Scan Insertion and compression techniques to handle DRC Violations

Use of compression techniques in DFT is basically used for optimizing tester application timing (i.e: ATE Test Time) and data volume area. For optimizing these two factors, scan insertion and compression techniques are used in the DFT methodology in order to achieve high quality of testability for the IC(SoC/ASIC) design at a low cost.

As the development of lower geometry design results increases in power density and heat dissipation which causes a reduction in reliability and damages in ICs. For preventing these power and heat dissipation issues, DFT engineers opt clock gating, voltage shut-offs, and other methods operated in the functional mode with controllability and observability. In order to manage this controllability (Controlling the change of signal value to Logic values required in the input) and observability (Observe the changing value in to the required logic value at the output) in functional mode, DFT Scan insertion and compression is proposed in node design to handle DRC violations at the same time.

In this technique, DFT engineers will first focus on two major aspects, i.e, scan flops conversion in the design and DRC violations. During design, if there are any DRC violations, that are identified then it can be fixed using Verilog commands. After fixing the DRCs, scan flops chain need to be created, which consist of the number of scan flops and a number of patterns (Logical signal combinations) in single-chain. Hence, scan compression is performed for decreasing the pattern length and memory usage. After inserting the scan compression logic again, check and fix the DRCs and the number of the scan flop stitched in the single chain can decided by the compression ratio. This scan insertion and compression has been implemented using the synopsis tool design compiler.

3. Low power design and management techniques in DFT

As chip size continues to shrink, low power design is a key issue but need to be focused on design for testability during functional operations simultaneously. DFT and lower power design challenges are much related to each other. DFT is applied to power management circuitries using power test access mechanism in order to improve power dissipation during ATPG (Automatic test pattern generation).

Let’s take a look at few low power management techniques mentioned below [i-v]:

i: Power domain connected with functional blocks: The device is implemented by including multiple functional blocks. Each block can be independently power-driven (up or down) by controlling the power switches connected to each functional block for power supply.

ii: Multiple supply voltages through level shifters: Depending on functional operation phase conditions, a power domain is connected through level shifters on signals that go from one voltage level to another. Without, level shifters voltage supply can never be sampled properly (with the right value). The reason behind adding level shifters is to ensure that functional operational blocks at different voltage supply will operate correctly when integrated together on a system-on-chip.

iii. Isolation logic cells: As power is gated off, the output value will start to float to an unknown value which gives incorrect values to the power domain. In order to overcome the issue of unknown floating values, DFT isolates such floating values and gives Logic 0 (ISO 0) or Logic 1 (ISO 1). These cells act like a buffer, which give constant values to the power blocks.

iv. Retention cells: Retention cells is a special flop state retention power gating (SRPG) cell, is used to retain the state of power domain before it gets shut off. This helps in shutdown leakage savings and power-up recovery.

v. Clock gating: This technique is applied to reduce the power dissipation in the power-on domain through clock pulse blockage dynamically to reach a set of chip elements. This helps to improve the efficiency and flexibility of power usage during functional operations

4. Handling of multiple fault categories for lower technology nodes during the DFT process

i. Processing fault: During fabrication of small ICs, there can be multiple issues that can take place like– missing the connection, creation of parasitic components, breakdown of oxidation layer, etc.

ii. Multiple defects: This is considered under bulk defects on the based element (The component from which the IC will be created.) –Cracks in the base element. The imperfection of IC crystalElement’s surface impurities.

iii. Time dependent failures: There are two faults that can occur when ICs lose their actual properties i.e.Dielectric failure: When the voltage is applied to the ICs and if the voltage applied exceeds, the IC may fail.

iv. Electromigration: Decay occurs when the voltage is applied repeatedly, and in such cases ICs may not be able to bear the capacity of the voltage, which may result in failure.

v. Packaging failure: Two conditions that arise during packaging of ICs i.e. contact of the logical signal degrades and leakage of packaging seal.

vi. Bridging faults: Bridging faults are also known as short circuit faults. If there are any defects on the PCB board that can be- lose or bare-wires, shortening of pins and others, needs to be corrected or else this may lead to circuit failures.

vii. Transient faults: This fault is caused by power supply fluctuation, which is non-repairable and may cause physical damage to hardware.

viii. Intermittent fault: This fault is also known as recurring fault because they reappear and disappear on a regular basis when power applied to ICs. This happens due to loose connection, partially defective gate components, poor circuit design, components which cannot generate their respective output.

ix. Delay fault: Output comes after a significant delay

x. Functional fault: Inaccurate functioning of the system at transistor level fault and logic gate level fault.

5. Test-point insertion for better test coverage in design for testability model

Testing point (TP) insertion is another way to solve the test problems in the circuit. TPs provide extra input and output to internal parts of the circuit. With the help of extra inputs/outputs, it becomes easy for a DFT engineer to detect fault coverages by making uncontrollable logic controllable, and unobservable logic observable that are hard-to-test for on-chip testing.

Test coverage insertion and efficient design testing flow are the key standards for circuit design quality when engineers use DFT techniques.

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Komal Chauhan works as a Digital Marketing Senior Executive at eInfochips where she supports digital marketing activities for various verticals - aerospace, DevOps, technical debt, semiconductor and silicon partnerships.