IP Portfolio-High speed chip-to-chip interface protocol

An advanced high speed chip-to-chip interface protocol with scalable bandwidth, low latency, and reliable data transfer over the link. The new generation supports up to 1.2 Tbps of bandwidth and support for NRZ and PAM4 connections. Interlaken IP uses multiple applications including NPU, traffic management, and switches. Open-Silicon, a SiFive company, is the founder of the Interlaken Alliance and supports Interlaken IP and silicon with 75 Tier 1 customers in various technologies and platforms.

The IP portfolio includes a support platform supporting up to 1.2 Tbps (64,000 channels and 48 SerDes paths) using multiple transceiver speeds and an error-correction (FEC) engine.

Expanding on the 8th generation of its Interlaken IP core, SiFive now features low latency versions of Chip-to-Chip and Die-to-Die Interlaken IP connections used in many applications. Cutting-edge technologies such as high-performance computing (HPC) clusters, AI/ML chip clusters, IoT edge devices, network and switch networks require high-speed data transfer from chip to chip with low latency. Interlaken-LL includes a support platform that supports up to 256 Gbps. OpenFive, a provider of silicon-centric solutions that can be configured with discrete IP, announced today the release of a new Die-to-Die (D2D) interface IP portfolio to serve based on the next generation of chipsets for Networking, HPC and AI marketing..

With recent advances in package technology and the increasing cost per unit area and new edge, it is beneficial to combine multiple dies, or chips, in one package with a silicon-based interposer or substrate.. To enable different connectivity for different markets, OpenFive Die-to-Die IP connectivity is a key enabler. OpenFive's 1st Generation Die-to-Die IP is designed to provide low-latency control to work with SerDes-based connectivity between two dies. OpenFive Die-to-Die IP is designed to allow SoC architects to connect chip stacks to XSR/VSR/SR based on SerDes while adopting customer-specific interfaces, or Arm® AMBA® AXI.

OpenFive's die-to-die controller provides low latency and scalable throughput to meet bandwidth requirements of several terabits with a single controller. Optional low latency Forward Error Correction (FEC) IP engines can help achieve a low Bit Error Rate (BER) depending on the characteristics of the channel connecting the two pages.

"We achieved throughput of>2 Tbps with latency of tens of nanoseconds end-to-end with a leading HPC client," said Mohit Gupta, SVP and General Manager, IP Business Unit, OpenFive. "Furthermore, by working with our main SerDes partners, we can provide a complete subsystem solution for their needs."

OpenFive is uniquely positioned with more than a decade of experience delivering solutions for networking, security and AI products with Interlaken IP for chip-to-chip connectivity, combined with ASIC-based experience and 2.5D for HBM2E-based products.

OpenFive will continue to expand its IP Die-to-Die portfolio for additional PHY-based architectures in the future as they become available. OpenFive is SiFive's proprietary custom silicon business and offers scalable and versatile IP SoCs for artificial intelligence, edge computing, HPC and networking solutions. The OpenFive portfolio includes Interlaken high-speed, low-speed, 400/800G Ethernet, high-bandwidth storage (HBM2/E), USB subsystem IP and die-to-interconnect IP -die for the next generation of different types of chipsets. separate. products. OpenFive's end-to-end expertise in architecture, design integration, software, silicon support, and manufacturing delivers high-quality silicon, with immediate results.

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