MCU CSR interface-SERDES interface-PHY with PIPE interface

SiFive provides comprehensive USB management and host services to devices. They are connected to our partners on many bases and together. MCU CSR interface, FPGA board is available for demonstration and example use.

• Compatible with USB 3.1 Gen 2 specification, PIPE USB 3.1 interface
• Supports 32/64 data bus width
• AXI, AHB standard bus
• Supports 32/64/128 data bus
• Supports all USB 3.1 power off models
• Supports Ccontrol, bulk, Iiochronous, and pause transactions
• Extensive support for end-to-end streaming
• The device can be configured up to 15 IN and 15 OUT terminals
• Number of configurable endpoints

Variable end FIFO for optimal memory usage

• SRAM interface connection for FIFO
• Well integrated DMA control

Advanced planning

• Compliant with the USB 3.1 Annex E standard
• Supports Gen 1 (5G) and Gen 2 (10G) speeds
• Supports low power states
• Supports MCU CSR interface to drive ASIC control and status register
• Supports PCS concept with 8b/10b for Gen1 and 128b/132b for Gen2 support
• Supports SErdES interface
• Optional external PHY support with PIPE interface
• SRIS walk
• Bypass" and "local loopback" supported
• Recommendation to analyze the main activities, including internal errors
• Support for connection monitoring
• The PIPE control signal can be configured through the CSR interface
• Basic loopback support for output analysis
• Option to create LFPS mode in debug mode

The embedded HBM controller and HBM PHY subsystem solutions support the HBM3, HBM2E and HBM2 JEDEC specifications for various technologies and base stations. As a leading proponent of 2.5D and 3D ASIC design technology and leveraging its experience gained from the industry's first successful demonstration of multiple 2.5D SiP SoCs, OpenFive plays an important role in bringing industry-leading applications Exploit HBM 3D DRAM technology.

The Die-to-Die IP Subsystem is targeted for various chip solutions in wired communications, AI and HPC applications. Due to recent advances in packaging technology, it is possible to transfer high-speed signals in a package that combines multiple losses or in an interposer or in an organic substrate. Die-to-Die Interposer I/O offers unique value propositions in terms of low-density, high-speed, and low-density connections, providing fast insertion times. Matrix-to-Matrix Interposer I/O

• Programmable CMOS I/O
• 3.2 Gbps/1.6 GHz DDR with power input
• Support for interposer trace lengths up to 5mm for over 3.2Gbps daily rate per pin
• The lamp conforms to the JEDEC HBM3/2E/2 specification
• Low latency management features
• Various receiver options

IP D2D PHY key scheme

• The D2D PHY signal is asymmetrical (Single Duplex) and depends on the electrical I/O of the HBM memory.
• Each channel has 42 Tx/Rx signal pairs working at a processing speed of up to 16 Gbps contributing up to ~1.75 Tbps/mm.
• Supports channel lengths of up to 5 mm and sub 5 ns latency (other packages available)
• Best in industry with less than 0.5 pJ/bit power consumption
• Added PLL to support differential clock transmission
• Independent startup and ranking system
• No forward error correction (FEC) IP requires that the signal support a channel BER of up to 1E-21
• Programmable output driver, compatible with different similar wire specifications in the industry.

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